1. Field of Invention
The present invention generally relates to a liquid crystal display (LCD) and thin film transistor (TFT) array substrate thereof. More particularly, the present invention relates to a liquid crystal display and thin film transistor array substrate thereof including a peripheral circuit region with terminal-narrowed shield lines.
2. Description of Related Art
In recent years, with great advance in the fabricating technique of electrical-optical and semiconductor devices, flat panel displays (FPDs), such as liquid crystal displays (LCDs), have been developed. Due to the advantageous features of LCDs, for example, low operation voltage, no harmful radiation, light weight, and compact size, LCDs replace the conventional Cathode Ray Tube (CRT) monitors and become mainstream.
FIG. 1 is a simplified cross-sectional view of a conventional liquid crystal display module. The liquid crystal display module shown in FIG. 1 comprises a thin film transistor array substrate 110, a color filter substrate 120, a black matrix layer 122 thereon, a sealant 130, a liquid crystal layer 140, polarizing films 152, 154 and an outer frame 160. The black matrix layer 122 is disposed on the color filter substrate 120. The sealant 130 is disposed between the color filter substrate 120 and the thin film transistor array substrate 110. The liquid crystal layer 140 is disposed within the space bounded by the color filter substrate 120, the thin film transistor array substrate 110 and the sealant 130. Furthermore, the polarizing films 154, 152 are disposed on other sides of the thin film transistor array substrate 110 and the color filter substrate 120, respectively. The outer frame 160 is disposed on the polarizing film 152. In addition, the thin film transistor array substrate 110 can be divided into a pixel region 110a and a peripheral circuit region 110b. The peripheral circuit region 110b has a plurality of lead lines 112 therein for connecting pixels in the pixel region 110a and peripheral circuits in the peripheral circuit region 110b. 
In a drop filling (ODF) process for forming the liquid crystal layer 140, if the sealant 130 is non-uniformly radiated by ultraviolet, the incompletely hardened sealant 130 may contaminate the liquid crystal 140. For this reason, the black matrix layer 122 on the color filter substrate 100 is slightly shrunk towards the center of the panel. However, because of the slight shrink of the black matrix layer 122, an area with light of leakage 170 is formed between the black matrix layer 122 and the sealant 130. In addition, there is no shield between the lead lines 112 within the peripheral circuit region 110b. Hence, light 180 emitted from the back light module may pass through the gaps between the lead lines 112, and light-leakage occurs at the junction between the outer frame 160 and the thin film transistor array substrate 110.
Therefore, in a prior solution, a shield layer, made of a first metal layer (M1) and a second metal layer (M2), is between the lead lines. FIG. 2 shows a partial top view of the peripheral circuit region of the thin film transistor array substrate. Referring to FIG. 2, each of a plurality of shield lines M10, made of the first metal layer, is disposed between two source lines S10, each made of the second metal layer. For leakage prevention, the shield line M10 is partially overlapped with two adjacent source leads S10. However, in case of particle contamination or static discharge, shorts occur at the overlap, for example, pointed by an arrow A10 in FIG. 2, between the shield line M10 and the source line S10. If so, a corresponding row of pixels is called a “bright line”, and the panel is not qualified.